(1) Field of the Invention
The present invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of fabricating dual-metal transistors having different work functions in the fabrication of integrated circuits.
(2) Description of the Prior Art
It is anticipated that a single metal gate with mid-gap work function values will not be suitable for CMOS applications due to buried channel effects. By using a single metal gate for both NMOSFET and PMOSFET, the threshold voltage becomes too high for both types of transistors. In order to achieve a lower threshold voltage, additional implantation is required and this will result in buried channel effects. The short channel effect control will then be degraded. However, with dual metal gates having different work functions, additional implantation is not required. That is, one electrode with a lower work function will be used in the NMOSFET while another electrode with a higher work function will be used for the PMOSFET. That means that the threshold voltage for NMOSFET and PMOSFET can be tailored independently. It is desired to maintain the conventional CMOS process flow in the dual metal gate process.
U.S. Pat. No. 6,043,157 to Gardner et al shows a process for forming dual gates where one gate is polysilicon and the other gate is metal. U.S. Pat. No. 6,087,231 to Xiang et al discloses a dummy gate process where amorphous gates doped with different dopants are formed. U.S. Pat. No. 6,083,836 to Rodder teaches a dummy gate process where two gates are formed. For example, one gate is polysilicon and the other is aluminum. U.S. Pat. No. 5,266,519 to Iwamoto teaches oxidation of a metal film to be used as an anti-plating mask.
Accordingly, a primary object of the invention is to provide a process for forming dual metal gates for CMOS transistors in the fabrication of integrated circuits.
A further object of the invention is to provide a process for forming dual-metal gate CMOS transistors having different work functions in the fabrication of integrated circuits.
Another object of the invention is to provide a process for forming dual-metal gate CMOS transistors where one gate comprises a metal and the other gate comprises the metal""s oxide.
Yet another object of the invention is to provide a process for forming dual-metal gate CMOS transistors comprising a metal and the metal oxide.
A still further object of the invention is to provide a process for forming dual-metal gate CMOS transistors comprising a first metal oxide and a second metal oxide wherein the metal is the same in both gates and the oxide concentration is different.
In accordance with the objects of the invention, a method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A gate dielectric layer is formed overlying the semiconductor substrate in each of the active areas. A metal layer is deposited overlying the gate dielectric layer. Oxygen ions are implanted into the metal layer in a first area to form an implanted metal layer and the implanted metal layer is oxidized to form a metal oxide layer. Thereafter, the metal layer and the metal oxide layer are patterned to form a metal gate in a second area and a metal oxide gate in the first area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The metal oxide may have a higher or lower work function depending on the metal used. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a second method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A dummy gate is formed in each of the active areas. The dummy gates are covered with a dielectric layer which is planarized whereby a top surface of each of the dummy gates is exposed. The exposed dummy gates are removed, leaving gate openings to the semiconductor substrate. A gate dielectric layer is formed overlying the semiconductor substrate in each of the gate openings. A metal layer is deposited within the gate openings to form metal gates. Oxygen ions are implanted into the metal gate only in a first area to form an implanted metal gate. The implanted metal gate is oxidized to form a metal oxide gate in the second area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The metal oxide may have a higher or lower work function depending on the metal used. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a third method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A gate dielectric layer is formed overlying the semiconductor substrate in each of the active areas. A metal layer is deposited overlying the gate dielectric layer. First oxygen ions are implanted into the metal layer in a first area to form an implanted metal layer and the implanted metal layer is oxidized to form a first metal oxide layer. Second oxygen ions are implanted into the metal layer in the second area to form an implanted metal layer and the implanted metal layer is oxidized to form a second metal oxide layer wherein the oxygen concentration in the second metal oxide layer is different from the oxide concentration in the first metal oxide layer. Thereafter, the first metal oxide layer and the second metal oxide layer are patterned to form a first metal oxide gate in the first area and a second metal oxide gate in the second area to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a fourth method for forming dual-metal gate CMOS transistors is achieved. First and second active areas of a semiconductor substrate are separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A dummy gate is formed in each of the active areas. The dummy gates are covered with a dielectric layer which is planarized whereby a top surface of each of the dummy gates is exposed. The exposed dummy gates are removed, leaving gate openings to the semiconductor substrate. A gate dielectric layer is formed overlying the semiconductor substrate in each of the gate openings. A metal layer is deposited within the gate openings to form metal gates. First oxygen ions are implanted into the metal gate only in a first area to form an implanted metal gate. The implanted metal gate is oxidized to form a first metal oxide gate in the second area. Second oxygen ions are implanted into the metal gate in the second area to form an implanted metal gate and the implanted metal gate is oxidized to form a second metal oxide gate wherein the oxygen concentration in the second metal oxide gate is different from the oxide concentration in the first metal oxide gate to complete formation of dual-metal gate CMOS transistors in the fabrication of an integrated circuit. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, a dual-metal gate CMOS integrated circuit device is achieved. The device comprises first and second active areas of a semiconductor substrate separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A metal gate in a first area overlies a gate dielectric layer, and a metal oxide gate in the second area overlies a gate dielectric layer wherein the metal in the metal gate is the same material as the metal in the metal oxide gate. The metal oxide may have a higher or lower work function depending on the metal used. The PMOS gate will be formed from the gate having the higher work function.
Also, in accordance with the objects of the invention, another dual-metal gate CMOS integrated circuit device is achieved. The device comprises first and second active areas of a semiconductor substrate separated by isolation regions. One of the active areas will be PMOS and the other will be NMOS. A first metal oxide gate in a first area overlies a gate dielectric layer, and a second metal oxide gate in the second area overlies a gate dielectric layer wherein the metal in the two gates is the same metal and the oxide concentration is different in each of the two gates. The PMOS gate will be formed from the gate having the higher work function.